The continuing popularity of portable electronic devices presents manufacturers with contrary goals. Battery capacity is dependent upon battery size and weight. Thus portable electronic devices could be made to operate a longer time between battery changes or recharging if these devices included heavier batteries with greater capacity. On the other hand, portable electronic devices would be more popular and more widely used if they were lighter. However, lighter weight translates into reduced battery capacity and reduced operating times. A large reduction in size of wireless telephones has taken place without significant reduction in operating times. While improvements in batteries have increased their capacity per unit weight, most of the improvement in operating time and reduction in device weight has come from improvements in the power consumption of the electronics. Many improvements have taken place in integrated circuit manufacture that have reduced the amount of power consumed by the electronics. Additional improvements have taken place by selective powering of portions of the electronics. To a large degree much of the advantage of selectively powering a microcontroller unit or a digital signal processor have already been realized by current state of the art devices. Thus manufacturers seek additional areas for power consumption reduction.
This additional area may be the system memory. Many portable electronic devices include substantial amounts of memory. Power savings may be gained by selectively powering either nonvolatile or volatile memory in respective active and standby operating modes. A circuit and method for optimally switching between active and standby operating modes is described by Haroun et al. in U.S. Pat. No. 6,151,262, which is incorporated herein by reference. Many circuit functions of volatile memory circuits such as dynamic random access memory (DRAM) and static random access memory (SRAM) may be suspended without loss of stored data. Moreover, some volatile memory in a wireless memory circuit may be used for computational storage, voice recognition, or other applications where data storage is only temporary. The process of fully powering these memory circuits typically requires much more time than that required for a memory access in the fully powered state. Thus, memory access time from a low power or standby state includes both the time required to power up the memory circuit and the normal access time. However, access times of these memories remains important, so it may not be feasible to completely shut the memory down to conserve power.
The inventors of the present invention have recently discovered that static random access memory cells power up in a state that minimizes leakage current. This phenomenon is explained with reference to TABLE I and FIGS. 4 and 5.
TABLE INormalizedIDQ0IDQ1Power UpIDQCell AreaMeanMeanMeanRatio0.843.65E−53.66E−54.30E−985000.896.33E−56.32E−56.00E−9105420.926.02E−56.02E−54.10E−9146830.929.00E−79.06E−73.90E−92320.959.03E−78.10E−73.90E−92201.005.80E−93.60E−92.90E−91.6
Referring to TABLE I, there are six rows representing different 6-T memory cells. These memory cells were fabricated by a complementary metal oxide semiconductor (CMOS) process. Mean entries in TABLE I are an average of measured data from fifty similar memory cells. The memory cells are arranged in order of normalized cell area as indicated in the left column. The top row, therefore, corresponds to the smallest cell area. The second column from the left is the measured quiescent current when the memory cells store a true zero data state (IDQ0). The third column from the left is the measured quiescent current when the memory cells store a true one data state (IDQ1). The fourth column from the left is the quiescent current for the memory cells of each row immediately after power up and before any data is written to the memory cells. The far right column is a ratio of the average of quiescent currents IDQ0 and IDQ1 divided by the quiescent current immediately after power up. The table shows that all except the last two rows have approximately the same quiescent current for either a true one or a true data state. The difference between IDQ0 and IDQ1 for the last two rows is slightly greater than for the previous four rows. For example, IDQ0 for the last row is 5.80E-9 A and IDQ1 is 3.60E-9. Thus, the IDQ1 current is about 60% greater than the IDQ0 current. By way of comparison, however, each entry in the fourth column is significantly less than either of the corresponding IDQ0 or IDQ1 current. The quiescent current immediately after power up for each type of memory cells, therefore, is significantly less than either IDQ0 or IDQ1. For example, the second and third rows show more than four orders of magnitude less current in their respective power up states than the mean of either IDQ0 or IDQ1. The fourth and fifth rows show more than two orders of magnitude less current in their respective power up states than the mean of either IDQ0 or IDQ1. Thus, the ratio in the far right column of average quiescent current (IDQ) to power up current in the fourth column decreases significantly with increasing cell area as indicated in the first column.
FIG. 4 illustrates a six-transistor (6-T) static random access memory cell. The memory cell includes P-channel transistors 400 and 402 and N-channel transistors 404 and 406 connected as a latch. N-channel pass gate transistors 408 and 410 couple bitline BL and complementary bitline/BL to respective data terminals of the memory cell. The heavy dotted line of N-channel transistor 406 indicates it has greater subthreshold leakage than N-channel transistor 404. This greater leakage may be due to many different factors including inconsistent polycrystalline silicon gate length, nonsymmetrical channel implants, nonsymmetrical source/drain implants, or other factors. In fact, the leakage of N-channel transistor 406 may be as much as two orders of magnitude or one hundred times greater than N-channel transistor 404. For example, a typical transistor such as N-channel transistor 404 may have a subthreshold leakage current of 1 nA. By way of comparison, a leaky transistor such as N-channel transistor 406 may have a subthreshold current of 10 nA. If residual data in a 256 K static random access memory with a 1.2 V power supply voltage leaves half of the data bits in a high leakage state, therefore, the memory array alone will dissipate 1.4 mW more power than if the entire array were in a low leakage state.
During power up when the wordline WL is off, power supply voltage Vdd is applied to the sources of P-channel transistors 400 and 402. Current flows through the P-channel transistors to common drain terminals 412 and 414, respectively. Since N-channel transistor 406 has a greater leakage current than N-channel transistor 404, however, terminal 414 has a lower voltage than terminal 412. As power supply voltage Vdd increases, the voltage at terminal 412 exceeds the threshold voltage of N-channel transistor 406 while the voltage at terminal 414 is still below the threshold voltage of N-channel transistor 404. Thus, N-channel transistor 406 becomes increasingly conductive and pulls terminal 414 even lower. This lower voltage at terminal 414 turns on P-channel transistor 400 and keeps N-channel transistor 404 off. This drives terminal 412 even higher, turning off P-channel transistor 402 and turning on N-channel transistor 406 even more. This regenerative effect continues as power supply voltage Vdd increases. When power supply voltage Vdd reaches a final value, therefore, terminal 414 is held at zero volts or ground and terminal 412 is held at power supply voltage Vdd. In this state, transistors 400 and 406 are both on. The leakage of the memory cell, therefore, is controlled by transistors 402 and 404, both of which are less leaky than transistor 406.
Referring now to FIG. 5, there is another 6-T static random access memory cell. This memory cell is similar to the memory cell of FIG. 4 except that the P-channel transistor 500 has a greater leakage current than P-channel transistor 502 as indicated by the heavy dotted line. N-channel transistors 504 and 506 have approximately the same leakage current. When power supply voltage Vdd is applied during power up, therefore, P-channel transistor 500 produces a relatively higher voltage at terminal 512 than the voltage at terminal 514. As power supply voltage Vdd increases, this relatively higher voltage turns on N-channel transistor 506 while N-channel transistor 504 is still off. N-channel transistor 506, therefore, pulls terminal 514 even lower, thereby turning on P-channel transistor 500 and holding N-channel transistor 504 off. The increasingly conductive P-channel transistor 500 drives terminal 512 higher, thereby turning off P-channel transistor 502 and turning on N-channel transistor 506 even more. When power supply voltage Vdd reaches a final value, therefore, terminal 514 is held at zero volts or ground and terminal 512 is held at power supply voltage Vdd. In this state, transistors 500 and 506 are both on. The leakage of the memory cell, therefore, is controlled by transistors 502 and 504, both of which are less leaky than transistor 500.
Memory cells of the prior art did not comprehend this pattern sensitive difference in quiescent current. Quiescent power dissipation of these prior art memory cell arrays was determined by the existing data state of each memory cell during standby operation. Random data states of the memory cells might result in power dissipation similar to all-zero or all-one data states. This quiescent power dissipation, however, might be much greater than an all-zero or all-one data pattern. The worst case quiescent power dissipation of prior art memory arrays corresponds to a data state opposite the power up data state. This worst power dissipation may be an order of magnitude greater than either the all-zero or all-one quiescent power dissipation.
The present invention describes a circuit and method to advantageously incorporate this power saving phenomenon in a portable electronic device such as a telephone handset, a handheld computer, a portable video game, or other battery powered device to greatly reduce standby current. The reduced standby current in the static random access memory array prolongs battery life and operating time, resulting in less frequent battery recharging.